The demand for greater circuit density and higher performance in Complementary Metal Oxide Semiconductor (CMOS) transistors is driving the gate length (LG) to a smaller dimension that is sub −100 nm in size in advanced technologies. Unfortunately, a reduced gate length aggravates the problems of gate depletion, high gate resistance, high gate tunneling leakage current, and boron penetration from a p+ doped gate into the channel region that are associated with polysilicon gates. To reduce the high gate resistance and gate depletion problems, the active dopant density in the polysilicon gate must be increased to a level that is greater than 1.87×1020 ions/cm3 in a CMOS technology where LG=25 nm for the polysilicon gate depletion layer to be less than 25% of the equivalent oxide thickness (EOT). This requirement presents a tremendous challenge since the active polysilicon dopant density at the interface of the gate and gate dielectric layer is saturated at 6×1019 ions/cm3 and 1×1020 ions/cm3, respectively. Insufficient active dopant density in the gate causes a significant voltage drop across the gate depletion layer and increases the EOT. As a result, gate capacitance in the inversion regime and inversion charge density (drive current) is reduced or a lower effective gate voltage occurs, thus compromising device performance.
Because of the shortcomings of polysilicon gates, there is immense interest in metal gate technology which has the advantages of eliminating gate depletion and boron penetration issues and lowering gate sheet resistance. Furthermore, the gate material is much more conductive than conventional heavily doped polysilicon gates. Examples of conductive materials used in metal gate technology are metals such as W and Mo, metal silicides including nickel silicide and cobalt silicide, and metallic nitrides such as TiN and WN.
One attractive approach for implementing a metal gate in a transistor device is to employ a silicidation process that completely consumes a conventional polysilicon gate electrode which is converted to a silicide that contacts the gate dielectric layer. Methods of forming fully silicided gate electrodes for transistors are described in a paper by B. Tavel et. al., entitled “Totally silicided (CoSi2) polysilicon: a novel approach to very low-resistive gate without metal CMP or etching”, published at the International Electron Device Meeting (IEDM), Wash. D.C., 2001, pp. 825-828.
A prior art process of forming a fully silicided gate electrode is shown in FIGS. 1a-1b where the silicidation of the gate and the source/drain regions is performed in one process step. Referring to FIG. 1a, a metal film 8 is deposited over a transistor structure having a polysilicon gate electrode 3, gate dielectric layer 2, and sidewall spacers 7 in addition to a source region 4, a drain region 5, and a channel 6 formed in a substrate 1. Referring to FIG. 1b, an anneal is performed to effect the silicidation process and converts the polysilicon gate into a silicide gate 9a. Additionally, a thick silicide region 9b is formed in source/drain regions 4, 5 which is undesirable since it leads to a transistor that suffers from a high source or drain leakage current.
In silicon-on-insulator (SOI) technology, the source/drain regions are formed above an insulator layer, allowing a significant reduction in the source and drain depletion capacitance. In FIGS. 2a-2b, a prior art method of forming a fully silicided gate in a transistor based on SOI technology is depicted. Referring to FIG. 2a, a metal film 18 is deposited over a transistor structure having a polysilicon gate electrode 13, gate dielectric layer 12, and sidewall spacers 17 in addition to a source region 14, a drain region 15, and a channel 16 formed on an insulating layer 11 on a substrate 10. Referring to FIG. 2b, an anneal is performed to effect the silicidation process and form thick silicide regions 19b in addition to the silicided gate 19a. Note that the contact area 20 between source/drain regions 14, 15 and silicided regions 19b is reduced in size which leads to a high contact resistance. The high series resistance associated with fully silicided source and drain regions must be overcome before SOI technology is implemented in manufacturing.
A recent improvement in the design of transistor devices involves raised source and drain regions which increases the thickness of the source and drain regions available for the silicidation process and lowers sheet resistance of the source and drain regions. An example of elevated source/drain regions that are combined with a metal gate electrode is found in U.S. Pat. No. 6,284,609 in which a doped epitaxial growth serves as a raised source/drain region. A metal gate is enclosed on the sides and bottom by a gate oxide layer.
In U.S. Pat. No. 6,518,154, two different metal gates are formed on a substrate, one on a p-type (PMOS) transistor and one on an n-type (NMOS) transistor. Spacers are fabricated after the gates are formed.
Similarly, in U.S. Pat. No. 6,545,324, two different metal gate transistors are formed on a substrate. The first metal gate is comprised of a first metal and the second metal gate which is thicker includes a first metal and a thin layer of a second metal.
A silicide gate transistor is described in U.S. Pat. No. 6,465,309 in which a dummy gate between two spacers is removed. A silicon oxynitride gate dielectric layer, an amorphous silicon layer, and a metal layer are sequentially deposited to fill the opening. An anneal at 400° C. to 800° C. affords a fully silicided gate electrode.
In related prior art found in U.S. Pat. No. 6,475,874, a recess formed by removing a dummy gate between two spacers is partially filled with a high k dielectric layer and an amorphous silicon layer. After a chemical mechanical polish (CMP) step, a metal such as nickel is deposited and a low temperature silicidation is performed.
A fully depleted FET with raised source/drain regions is disclosed in U.S. Pat. No. 6,406,951 and in U.S. Pat. No. 6,551,885 in which a recess is formed between raised source/drain regions by removing an insulator layer. A gate dielectric layer is conformally deposited in the recess followed by formation of spacers along the sidewalls and then depositing a conductive material which is subsequently planarized. However, silicidation occurs only in the raised source/drain regions.
In U.S. Pat. No. 6,525,378, raised source/drain regions are formed adjacent to spacers that are on opposite sides of a gate electrode and dielectric layer. During silicidation of the raised source/drain regions, only the top portion of the gate electrode forms a silicide.
Although the prior art includes several examples of transistors that have at least two of the technology elements that include SOI substrates, raised source/drains, and fully silicided recessed gates, to our knowledge there is no method that incorporates all three elements into a single fabrication scheme. Therefore, a transistor based on these three technology elements is needed in order to meet the requirements of high performance devices that have sub −100 nm gate lengths.